哈哈哈哈哈操欧洲电影,久草网在线,亚洲久久熟女熟妇视频,麻豆精品色,久久福利在线视频,日韩中文字幕的,淫乱毛视频一区,亚洲成人一二三,中文人妻日韩精品电影

0
  • 聊天消息
  • 系統(tǒng)消息
  • 評論與回復(fù)
登錄后你可以
  • 下載海量資料
  • 學(xué)習(xí)在線課程
  • 觀看技術(shù)視頻
  • 寫文章/發(fā)帖/加入社區(qū)
會員中心
創(chuàng)作中心

完善資料讓更多小伙伴認(rèn)識你,還能領(lǐng)取20積分哦,立即完善>

3天內(nèi)不再提示

Xilinx FPGA里面的AXI DMA IP核的簡單用法

C29F_xilinx_inc ? 來源:賽靈思 ? 作者:賽靈思 ? 2022-02-16 16:21 ? 次閱讀
加入交流群
微信小助手二維碼

掃碼添加小助手

加入工程師交流群

FPGA里面,AXI DMA這個(gè)IP核的主要作用,就是在Verilog語言和C語言之間傳輸大批量的數(shù)據(jù),使用的通信協(xié)議為AXI4-Stream。

Xilinx很多IP核都是基于AXI4-Stream協(xié)議的,例如浮點(diǎn)數(shù)Floating-point IP核,以及以太網(wǎng)Tri Mode Ethernet MAC IP核。要想將Verilog層面的數(shù)據(jù)搬運(yùn)到C語言里面處理,就要使用DMA IP核。

本文以浮點(diǎn)數(shù)Floating-point IP核將定點(diǎn)數(shù)轉(zhuǎn)換為浮點(diǎn)數(shù)為例,詳細(xì)講解AXI DMA IP核的使用方法。

浮點(diǎn)數(shù)IP核的輸入輸出數(shù)據(jù)都是32位,協(xié)議均為AXI4-Stream。C語言程序首先將要轉(zhuǎn)換的定點(diǎn)數(shù)數(shù)據(jù)通過DMA發(fā)送給浮點(diǎn)數(shù)IP核,浮點(diǎn)數(shù)IP核轉(zhuǎn)換完成后再通過DMA將單精度浮點(diǎn)數(shù)結(jié)果發(fā)回C語言程序,再通過printf打印出來。

定點(diǎn)數(shù)的數(shù)據(jù)類型為int,小數(shù)點(diǎn)定在第四位上,即:XXXXXXX.X。整數(shù)部分占28位,小數(shù)部分占4位。

轉(zhuǎn)換后浮點(diǎn)數(shù)的數(shù)據(jù)類型為float,可以用printf的%f直接打印出來。

工程下載地址:https://pan.baidu.com/s/1SXppHMdhroFT8vGCIysYTQ(提取碼:u7wf)

MicroBlaze C語言工程的建法不再贅述,請參閱:https://blog.csdn.net/ZLK1214/article/details/111824576

pYYBAGIMpo2AJqjNAAH_MWNrJUU622.png

首先添加Floating-point IP核,作為DMA的外設(shè)端:(主存端為BRAM)

poYBAGIMpo-ANZDbAAA_l0ntfqk097.png

poYBAGIMppCAJxSNAAEGvn8Va34201.png

pYYBAGIMppKAStvHAAEMJT25qmg379.png

poYBAGIMppSAJJnmAAD2VQEXRHw583.png

這里要注意一下,一定要勾選上TLAST,否則DMA接收端會出現(xiàn)DMA Internal Error的錯(cuò)誤:

pYYBAGIMppaAVBY2AAFE0VbVX3o575.png

下面是Xilinx DMA手冊里面對DMA Internal Error錯(cuò)誤的描述:

poYBAGIMppiAHRX6AACbAx3Wn-M539.png

添加AXI DMA IP核:

pYYBAGIMppqARPshAABNz_Q8C2c867.png

IP核添加好了,但還沒有連線:

pYYBAGIMppyAV16VAACq-RthNiM037.png

點(diǎn)擊Run Connection Automation,自動連接DMA的S_AXI_LITE接口

pYYBAGIMpp6AMfbJAAE2FppS-0I773.png

poYBAGIMpqKAWFqEAAKoYpB4afY616.png

pYYBAGIMpqSALYymAAEFOXj7KkI879.png

pYYBAGIMpqaAPHUkAAFJHM4rMQI008.png

poYBAGIMpqmAUl7LAAEg29w2F28228.png

自動連接浮點(diǎn)數(shù)IP核的時(shí)鐘引腳:

pYYBAGIMpquAEl5bAAFqfrxqB3Q110.png

poYBAGIMpq-ASKUlAAQhpFjGMvY547.png

poYBAGIMprGAOAtYAAFr6mSyUyY366.png

pYYBAGIMprOAElDjAAFLHFr0bfQ712.png

pYYBAGIMprWAKbr4AAKKtr6QNo8705.png

添加BRAM控制器

poYBAGIMpraAWb5LAAAQUOLl1YU793.png

pYYBAGIMpriAEAvhAAG3KfwYg_8873.png

最終的連線結(jié)果:

pYYBAGIMprqAfAw4AAK-1KrBJC4019.png

修改新建的BRAM的容量為64KB:

pYYBAGIMpryARkB4AAFxBvZe0Bg340.png

pYYBAGIMpr-AbUYfAAGA3kbuYQ8313.png

最終的地址分配方式:

poYBAGIMpsGAOpbRAAF_bEy5vaE460.png

保存Block Design,然后生成Bitstream:

pYYBAGIMpsOATBaGAAEszSUAiCM178.png

Bitstream生成后,導(dǎo)出xsa文件:

poYBAGIMpsSADsPbAAD1JA0uxRY519.png

Vitis Platform工程重新導(dǎo)入xsa文件:

poYBAGIMpsaARsBwAACII8fJ-zA463.png

poYBAGIMpsmAVEo0AAT3WAEPq1E727.png

修改C程序(helloworld.c)的代碼:

(這里面XPAR_BRAM_2_BASEADDR最好改成0xc0000000,因?yàn)樯傻膞parameters.h配置文件里面BRAM號可能有變化)
/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/

/*
* helloworld.c: simple test application
*
* This application configures UART 16550 to baud rate 9600.
* PS7 UART (Zynq) is not initialized by this application, since
* bootrom/bsp configures it to baud rate 115200
*
* ------------------------------------------------
* | UART TYPE BAUD RATE |
* ------------------------------------------------
* uartns550 9600
* uartlite Configurable only in HW design
* ps7_uart 115200 (configured by bootrom/bsp)
*/

#include
#include
#include "platform.h"

// DMA無法通過AXI Interconnect訪問Microblaze本身的BRAM內(nèi)存
// 只能訪問掛接在AXI Interconnect上的內(nèi)存
#define _countof(arr) (sizeof(arr) / sizeof(*(arr)))
typedef struct
{
int numbers_in[40];
float numbers_out[40];
} BRAM2_Data;

static BRAM2_Data *bram2_data = (BRAM2_Data *)XPAR_BRAM_2_BASEADDR;
static XAxiDma xaxidma;

int main(void)
{
int i, ret = 0;
XAxiDma_Config *xaxidma_cfg;

init_platform();

printf("Hello World\n");
printf("Successfully ran Hello World application\n");

// 初始化DMA
xaxidma_cfg = XAxiDma_LookupConfig(XPAR_AXIDMA_0_DEVICE_ID);
XAxiDma_CfgInitialize(&xaxidma, xaxidma_cfg);
ret = XAxiDma_Selftest(&xaxidma);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_Selftest() failed! ret=%d\n", ret);
goto err;
}

// 初始化DMA的輸入數(shù)據(jù)
printf("numbers_in=%p, numbers_out=%p\n", bram2_data->numbers_in, bram2_data->numbers_out);
for (i = 0; i numbers_in); i++)
{
bram2_data->numbers_in[i] = 314 * (i + 1);
if (i & 1)
bram2_data->numbers_in[i] = -bram2_data->numbers_in[i];
}

// DMA開始發(fā)送數(shù)據(jù) (Length參數(shù)的單位為字節(jié))
ret = XAxiDma_SimpleTransfer(&xaxidma, (uintptr_t)bram2_data->numbers_in, sizeof(bram2_data->numbers_in), XAXIDMA_DMA_TO_DEVICE);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_SimpleTransfer(XAXIDMA_DMA_TO_DEVICE) failed! ret=%d\n", ret);
goto err;
}

// DMA開始接收數(shù)據(jù)
ret = XAxiDma_SimpleTransfer(&xaxidma, (uintptr_t)bram2_data->numbers_out, sizeof(bram2_data->numbers_out), XAXIDMA_DEVICE_TO_DMA);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_SimpleTransfer(XAXIDMA_DEVICE_TO_DMA) failed! ret=%d\n", ret);
goto err;
}

// 等待DMA發(fā)送完畢
i = 0;
while (XAxiDma_Busy(&xaxidma, XAXIDMA_DMA_TO_DEVICE))
{
i++;
if (i == 200000)
{
// 必須確保DMA訪問的內(nèi)存是直接掛接在AXI Interconnect上的
// 否則這里會報(bào)DMA Decode Error的錯(cuò)誤 (the address request points to an invalid address)
printf("DMA Tx timeout! DMASR=0x%08lx\n", XAxiDma_ReadReg(xaxidma.RegBase + XAXIDMA_TX_OFFSET, XAXIDMA_SR_OFFSET));
goto err;
}
}
printf("DMA Tx complete!\n");

// 等待DMA接收完畢
i = 0;
while (XAxiDma_Busy(&xaxidma, XAXIDMA_DEVICE_TO_DMA))
{
i++;
if (i == 200000)
{
// floating-point IP核的配置里面一定要把A通道的tlast復(fù)選框勾選上, 使輸入端和輸出端都有tlast信號
// 否則s_axis_s2mm_tlast一直為0, DMA以為數(shù)據(jù)還沒接收完, 就會報(bào)DMA Internal Error的錯(cuò)誤
// (the incoming packet is bigger than what is specified in the DMA length register)
printf("DMA Rx timeout! DMASR=0x%08lx\n", XAxiDma_ReadReg(xaxidma.RegBase + XAXIDMA_RX_OFFSET, XAXIDMA_SR_OFFSET));
goto err;
}
}
printf("DMA Rx complete!\n");

err:
for (i = 0; i numbers_out); i++)
printf("numbers_out[%d]=%f\n", i, bram2_data->numbers_out[i]);

cleanup_platform();
return 0;
}

C程序的運(yùn)行結(jié)果:

pYYBAGIMpsuAAHqIAAOtyw3zrA4278.png

Hello World
Successfully ran Hello World application
numbers_in=0xc0000000, numbers_out=0xc00000a0
DMA Tx complete!
DMA Rx complete!
numbers_out[0]=19.625000
numbers_out[1]=-39.250000
numbers_out[2]=58.875000
numbers_out[3]=-78.500000
numbers_out[4]=98.125000
numbers_out[5]=-117.750000
numbers_out[6]=137.375000
numbers_out[7]=-157.000000
numbers_out[8]=176.625000
numbers_out[9]=-196.250000
numbers_out[10]=215.875000
numbers_out[11]=-235.500000
numbers_out[12]=255.125000
numbers_out[13]=-274.750000
numbers_out[14]=294.375000
numbers_out[15]=-314.000000
numbers_out[16]=333.625000
numbers_out[17]=-353.250000
numbers_out[18]=372.875000
numbers_out[19]=-392.500000
numbers_out[20]=412.125000
numbers_out[21]=-431.750000
numbers_out[22]=451.375000
numbers_out[23]=-471.000000
numbers_out[24]=490.625000
numbers_out[25]=-510.250000
numbers_out[26]=529.875000
numbers_out[27]=-549.500000
numbers_out[28]=569.125000
numbers_out[29]=-588.750000
numbers_out[30]=608.375000
numbers_out[31]=-628.000000
numbers_out[32]=647.625000
numbers_out[33]=-667.250000
numbers_out[34]=686.875000
numbers_out[35]=-706.500000
numbers_out[36]=726.125000
numbers_out[37]=-745.750000
numbers_out[38]=765.375000
numbers_out[39]=-785.000000

poYBAGIMps6AYy8nAAS7yU8SJ_8640.png

接下來講一下我們剛才禁用掉的Scatter Gather接口的用法。取消禁用后,之前的C代碼就不能運(yùn)行了。
之前沒有啟用Scatter Gather的時(shí)候,我們一次只能提交一個(gè)DMA請求,等這個(gè)DMA請求的數(shù)據(jù)傳輸完畢后,我們才能提交下一個(gè)DMA傳輸請求。
有了Scatter Gather接口,我們就可以一次性提交很多很多DMA請求,然后CPU去干其他的事情。這可以大大提高傳輸效率。
除此以外,Scatter Gather還可以將多個(gè)位于不同內(nèi)存地址的緩沖區(qū)合并成一個(gè)AXI4-Stream數(shù)據(jù)包傳輸。

下面的示例演示了如何利用Scatter Gather功能批量收發(fā)3組數(shù)據(jù)包。
啟用了Scatter Gather后,DMA里面多出了一個(gè)M_AXI_SG接口,點(diǎn)擊Run Connection Automation,連接到AXI Interconnect上:

pYYBAGIMptCAMQ6zAAKe7D5xcpo553.png

pYYBAGIMptKAF2XMAAZpvcPD86o959.png

Vivado工程Generate Bitstream,然后導(dǎo)出xsa文件?;氐絍itis后,必須把Platform工程刪了重建,不然XPAR_AXI_DMA_0_INCLUDE_SG的值得不到更新。

poYBAGIMptSAe0AnAADlJnJWhCw515.png

pYYBAGIMptaAS3wVAAbTkOJjG3o749.png

pYYBAGIMptiAXaiaAAg2skXUvyM504.png

原有的C程序不再可用,修改一下程序代碼
/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/

/*
* helloworld.c: simple test application
*
* This application configures UART 16550 to baud rate 9600.
* PS7 UART (Zynq) is not initialized by this application, since
* bootrom/bsp configures it to baud rate 115200
*
* ------------------------------------------------
* | UART TYPE BAUD RATE |
* ------------------------------------------------
* uartns550 9600
* uartlite Configurable only in HW design
* ps7_uart 115200 (configured by bootrom/bsp)
*/

#include
#include
#include "platform.h"

/* Xilinx的官方例程:C:\Xilinx\Vitis\2020.1\data\embeddedsw\XilinxProcessorIPLib\drivers\axidma_v9_11\examples\xaxidma_example_sg_poll.c */

// DMA無法通過AXI Interconnect訪問Microblaze本身的BRAM內(nèi)存
// 只能訪問掛接在AXI Interconnect上的內(nèi)存
#define _countof(arr) (sizeof(arr) / sizeof(*(arr)))
typedef struct
{
int numbers_in[40];
float numbers_out[40];
} BRAM2_Data;

typedef struct
{
uint8_t txbuf[640];
uint8_t rxbuf[640];
} BRAM2_BdRingBuffer;

static BRAM2_Data *bram2_data = (BRAM2_Data *)0xc0000000;
static BRAM2_BdRingBuffer *bram2_bdringbuf = (BRAM2_BdRingBuffer *)0xc0008000;
static XAxiDma xaxidma;

int main(void)
{
int i, n, ret = 0;
XAxiDma_Bd *bd, *p;
XAxiDma_BdRing *txring, *rxring;
XAxiDma_Config *cfg;

init_platform();

printf("Hello World\n");
printf("Successfully ran Hello World application\n");

// 初始化DMA
cfg = XAxiDma_LookupConfig(XPAR_AXIDMA_0_DEVICE_ID);
XAxiDma_CfgInitialize(&xaxidma, cfg);
ret = XAxiDma_Selftest(&xaxidma);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_Selftest() failed! ret=%d\n", ret);
goto err;
}

if (!XAxiDma_HasSg(&xaxidma))
{
printf("XPAR_AXI_DMA_0_INCLUDE_SG=%d\n", XPAR_AXI_DMA_0_INCLUDE_SG);
printf("Please recreate and build Vitis platform project!\n");
goto err;
}

// 初始化DMA的輸入數(shù)據(jù)
printf("[0] numbers_in=%p, numbers_out=%p\n", bram2_data[0].numbers_in, bram2_data[0].numbers_out);
printf("[1] numbers_in=%p, numbers_out=%p\n", bram2_data[1].numbers_in, bram2_data[1].numbers_out);
printf("[2] numbers_in=%p, numbers_out=%p\n", bram2_data[2].numbers_in, bram2_data[2].numbers_out);
for (i = 0; i {
bram2_data[0].numbers_in[i] = 314 * (i + 1);
bram2_data[1].numbers_in[i] = -141 * (i + 1);
bram2_data[2].numbers_in[i] = -2718 * (i + 1);
if (i & 1)
{
bram2_data[0].numbers_in[i] = -bram2_data[0].numbers_in[i];
bram2_data[1].numbers_in[i] = -bram2_data[1].numbers_in[i];
bram2_data[2].numbers_in[i] = -bram2_data[2].numbers_in[i];
}
}

// 配置DMA發(fā)送描述符
txring = XAxiDma_GetTxRing(&xaxidma);
n = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT, sizeof(bram2_bdringbuf->txbuf));
ret = XAxiDma_BdRingCreate(txring, (uintptr_t)bram2_bdringbuf->txbuf, (uintptr_t)bram2_bdringbuf->txbuf, XAXIDMA_BD_MINIMUM_ALIGNMENT, n);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingCreate(txring) failed! ret=%d\n", ret);
goto err;
}
printf("BdRing Tx count: %d\n", n);

ret = XAxiDma_BdRingAlloc(txring, 3, &bd);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingAlloc(txring) failed! ret=%d\n", ret);
goto err;
}

p = bd;
for (i = 0; i {
XAxiDma_BdSetBufAddr(p, (uintptr_t)bram2_data[i].numbers_in);
XAxiDma_BdSetLength(p, sizeof(bram2_data[i].numbers_in), txring->MaxTransferLen);
XAxiDma_BdSetCtrl(p, XAXIDMA_BD_CTRL_TXSOF_MASK | XAXIDMA_BD_CTRL_TXEOF_MASK);
XAxiDma_BdSetId(p, i);
p = (XAxiDma_Bd *)XAxiDma_BdRingNext(txring, p);
}

ret = XAxiDma_BdRingToHw(txring, 3, bd);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingToHw(txring) failed! ret=%d\n", ret);
goto err;
}

// 配置DMA接收描述符
rxring = XAxiDma_GetRxRing(&xaxidma);
n = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT, sizeof(bram2_bdringbuf->rxbuf));
ret = XAxiDma_BdRingCreate(rxring, (uintptr_t)bram2_bdringbuf->rxbuf, (uintptr_t)bram2_bdringbuf->rxbuf, XAXIDMA_BD_MINIMUM_ALIGNMENT, n);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingCreate(rxring) failed! ret=%d\n", ret);
goto err;
}
printf("BdRing Rx count: %d\n", n);

ret = XAxiDma_BdRingAlloc(rxring, 3, &bd);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingAlloc(rxring) failed! ret=%d\n", ret);
goto err;
}

p = bd;
for (i = 0; i {
XAxiDma_BdSetBufAddr(p, (uintptr_t)bram2_data[i].numbers_out);
XAxiDma_BdSetLength(p, sizeof(bram2_data[i].numbers_out), rxring->MaxTransferLen);
XAxiDma_BdSetCtrl(p, 0);
XAxiDma_BdSetId(p, i);
p = (XAxiDma_Bd *)XAxiDma_BdRingNext(rxring, p);
}

ret = XAxiDma_BdRingToHw(rxring, 3, bd);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingToHw(rxring) failed! ret=%d\n", ret);
goto err;
}

// 開始發(fā)送數(shù)據(jù)
ret = XAxiDma_BdRingStart(txring);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingStart(txring) failed! ret=%d\n", ret);
goto err;
}

// 開始接收數(shù)據(jù)
ret = XAxiDma_BdRingStart(rxring);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingStart(rxring) failed! ret=%d\n", ret);
goto err;
}

// 等待收發(fā)結(jié)束
n = 0;
while (n {
// 檢查發(fā)送是否結(jié)束
ret = XAxiDma_BdRingFromHw(txring, XAXIDMA_ALL_BDS, &bd);
if (ret != 0)
{
n += ret;
p = bd;
for (i = 0; i {
printf("DMA Tx%lu Complete!\n", XAxiDma_BdGetId(p));
p = (XAxiDma_Bd *)XAxiDma_BdRingNext(txring, p);
}

ret = XAxiDma_BdRingFree(txring, ret, bd);
if (ret != XST_SUCCESS)
printf("XAxiDma_BdRingFree(txring) failed! ret=%d\n", ret);
}

// 檢查接收是否結(jié)束
ret = XAxiDma_BdRingFromHw(rxring, XAXIDMA_ALL_BDS, &bd);
if (ret != 0)
{
n += ret;
p = bd;
for (i = 0; i {
printf("DMA Rx%lu Complete!\n", XAxiDma_BdGetId(p));
p = (XAxiDma_Bd *)XAxiDma_BdRingNext(rxring, p);
}

ret = XAxiDma_BdRingFree(rxring, ret, bd);
if (ret != XST_SUCCESS)
printf("XAxiDma_BdRingFree(rxring) failed! ret=%d\n", ret);
}
}

err:
for (i = 0; i printf("numbers_out[%d]=%f,%f,%f\n", i, bram2_data[0].numbers_out[i], bram2_data[1].numbers_out[i], bram2_data[2].numbers_out[i]);

cleanup_platform();
return 0;
}

程序運(yùn)行結(jié)果:

Hello World
Successfully ran Hello World application
[0] numbers_in=0xc0000000, numbers_out=0xc00000a0
[1] numbers_in=0xc0000140, numbers_out=0xc00001e0
[2] numbers_in=0xc0000280, numbers_out=0xc0000320
BdRing Tx count: 10
BdRing Rx count: 10
DMA Tx0 Complete!
DMA Tx1 Complete!
DMA Tx2 Complete!
DMA Rx0 Complete!
DMA Rx1 Complete!
DMA Rx2 Complete!
numbers_out[0]=19.625000,-8.812500,-169.875000
numbers_out[1]=-39.250000,17.625000,339.750000
numbers_out[2]=58.875000,-26.437500,-509.625000
numbers_out[3]=-78.500000,35.250000,679.500000
numbers_out[4]=98.125000,-44.062500,-849.375000
numbers_out[5]=-117.750000,52.875000,1019.250000
numbers_out[6]=137.375000,-61.687500,-1189.125000
numbers_out[7]=-157.000000,70.500000,1359.000000
numbers_out[8]=176.625000,-79.312500,-1528.875000
numbers_out[9]=-196.250000,88.125000,1698.750000
numbers_out[10]=215.875000,-96.937500,-1868.625000
numbers_out[11]=-235.500000,105.750000,2038.500000
numbers_out[12]=255.125000,-114.562500,-2208.375000
numbers_out[13]=-274.750000,123.375000,2378.250000
numbers_out[14]=294.375000,-132.187500,-2548.125000
numbers_out[15]=-314.000000,141.000000,2718.000000
numbers_out[16]=333.625000,-149.812500,-2887.875000
numbers_out[17]=-353.250000,158.625000,3057.750000
numbers_out[18]=372.875000,-167.437500,-3227.625000
numbers_out[19]=-392.500000,176.250000,3397.500000
numbers_out[20]=412.125000,-185.062500,-3567.375000
numbers_out[21]=-431.750000,193.875000,3737.250000
numbers_out[22]=451.375000,-202.687500,-3907.125000
numbers_out[23]=-471.000000,211.500000,4077.000000
numbers_out[24]=490.625000,-220.312500,-4246.875000
numbers_out[25]=-510.250000,229.125000,4416.750000
numbers_out[26]=529.875000,-237.937500,-4586.625000
numbers_out[27]=-549.500000,246.750000,4756.500000
numbers_out[28]=569.125000,-255.562500,-4926.375000
numbers_out[29]=-588.750000,264.375000,5096.250000
numbers_out[30]=608.375000,-273.187500,-5266.125000
numbers_out[31]=-628.000000,282.000000,5436.000000
numbers_out[32]=647.625000,-290.812500,-5605.875000
numbers_out[33]=-667.250000,299.625000,5775.750000
numbers_out[34]=686.875000,-308.437500,-5945.625000
numbers_out[35]=-706.500000,317.250000,6115.500000
numbers_out[36]=726.125000,-326.062500,-6285.375000
numbers_out[37]=-745.750000,334.875000,6455.250000
numbers_out[38]=765.375000,-343.687500,-6625.125000
numbers_out[39]=-785.000000,352.500000,6795.000000

審核編輯:符乾江

聲明:本文內(nèi)容及配圖由入駐作者撰寫或者入駐合作網(wǎng)站授權(quán)轉(zhuǎn)載。文章觀點(diǎn)僅代表作者本人,不代表電子發(fā)燒友網(wǎng)立場。文章及其配圖僅供工程師學(xué)習(xí)之用,如有內(nèi)容侵權(quán)或者其他違規(guī)問題,請聯(lián)系本站處理。 舉報(bào)投訴
  • FPGA
    +關(guān)注

    關(guān)注

    1663

    文章

    22491

    瀏覽量

    638809
  • Xilinx
    +關(guān)注

    關(guān)注

    73

    文章

    2205

    瀏覽量

    131798
收藏 人收藏
加入交流群
微信小助手二維碼

掃碼添加小助手

加入工程師交流群

    評論

    相關(guān)推薦
    熱點(diǎn)推薦

    Xilinx FPGA中的混合模式時(shí)鐘管理器MMCME2_ADV詳解

    FPGA 的浩瀚宇宙中,時(shí)鐘系統(tǒng)不僅是驅(qū)動邏輯運(yùn)轉(zhuǎn)的“心臟”,更是決定系統(tǒng)穩(wěn)定性與性能上限的“指揮棒”。對于 Xilinx 7 系列 FPGA 開發(fā)者而言,如果僅滿足于使用 Clocking Wizard
    的頭像 發(fā)表于 04-10 11:20 ?145次閱讀
    <b class='flag-5'>Xilinx</b> <b class='flag-5'>FPGA</b>中的混合模式時(shí)鐘管理器MMCME2_ADV詳解

    利用開源uart2axi4實(shí)現(xiàn)串口訪問axi總線

    microblaze和jtag-to-axi(jtag2axi)雖然也提供了訪問axi總線的能力,但是依賴于xilinx平臺。而uart-to-ax
    的頭像 發(fā)表于 12-02 10:05 ?2221次閱讀
    利用開源uart2<b class='flag-5'>axi</b>4實(shí)現(xiàn)串口訪問<b class='flag-5'>axi</b>總線

    RDMA設(shè)計(jì)6:IP架構(gòu)2

    擴(kuò)展的通用 IP ,在 RoCE v2 高速數(shù)據(jù)傳輸系統(tǒng)擔(dān)任網(wǎng)絡(luò)物理層的角色。其提供一組主 AXI-Stream 接口和一組從 AXI-Stream接口,用以傳輸網(wǎng)絡(luò)包。同時(shí) CMA
    發(fā)表于 11-26 10:24

    基于AXI DMA IP的DDR數(shù)據(jù)存儲與PS端讀取

    添加Zynq Processing System IP,配置DDR控制器和時(shí)鐘。7000系列的Zynq可以參考正點(diǎn)原子DMA回環(huán)測試設(shè)置。
    的頭像 發(fā)表于 11-24 09:25 ?3501次閱讀
    基于<b class='flag-5'>AXI</b> <b class='flag-5'>DMA</b> <b class='flag-5'>IP</b><b class='flag-5'>核</b>的DDR數(shù)據(jù)存儲與PS端讀取

    使用AXI4接口IP進(jìn)行DDR讀寫測試

    本章的實(shí)驗(yàn)任務(wù)是在 PL 端自定義一個(gè) AXI4 接口的 IP ,通過 AXI_HP 接口對 PS 端 DDR3 進(jìn)行讀寫測試,讀寫的內(nèi)存大小是 4K 字節(jié)。
    的頭像 發(fā)表于 11-24 09:19 ?3886次閱讀
    使用<b class='flag-5'>AXI</b>4接口<b class='flag-5'>IP</b><b class='flag-5'>核</b>進(jìn)行DDR讀寫測試

    RDMA設(shè)計(jì)4:技術(shù)需求分析2

    得出具體技術(shù)指標(biāo)如表1 所示。 表1 高速數(shù)據(jù)傳輸項(xiàng)目技術(shù)指標(biāo)表 基于以上性能指標(biāo),基于 FPGA 的 RoCE v2 IP具有以下特點(diǎn): (1)基于 IBTA 1.5 協(xié)議規(guī)范,支持 RoCE
    發(fā)表于 11-24 09:09

    Xilinx高性能NVMe Host控制器IP+PCIe 3.0軟控制器IP,純邏輯實(shí)現(xiàn),AXI4和AXI4-Stream DMA接口,支持PCIe 3.0和4.0

    )讀寫、DMA讀寫和數(shù)據(jù)擦除功能,提供用戶一個(gè)簡單高效的接口實(shí)現(xiàn)高性能存儲解決方案。NVMe AXI4 Host Controller IP讀寫的順序傳輸長度是RTL運(yùn)行時(shí)動態(tài)可配置的
    發(fā)表于 11-14 22:40

    NVMe高速傳輸之?dāng)[脫XDMA設(shè)計(jì)44:工程設(shè)計(jì)考量?

    。 基于 VC709 FPGA 的 Block Design 工程設(shè)計(jì)如圖 1 所示。 圖中 CPU 模塊中包含了 Xilinx 提供的 Microblaze CPU 軟以及一些內(nèi)存與復(fù)位模塊, 除時(shí)鐘
    發(fā)表于 11-12 09:52

    VDMA IP簡介

    VDMA端口信號 S_AXI_LITE:PS端可以通過AXI_LITE協(xié)議對IP進(jìn)行控制; S_AXIS_S2MM:視頻流(AXI
    發(fā)表于 10-28 06:14

    AXI GPIO擴(kuò)展e203 IO口簡介

    AXI GPIO簡介 AXI-GPIO是一種Xilinx公司開發(fā)的外設(shè)IP,可以連接到AXI總線上,并提供GPIO(General Purp
    發(fā)表于 10-22 08:14

    基于E203的DMA ip的使用

    1.BD設(shè)計(jì) 2.AXI DMA寄存器 編寫SDK代碼,需要根據(jù)xilinx的官方例程和dma ip使用手冊進(jìn)行寄存器的配置
    發(fā)表于 10-22 06:00

    FPGA利用DMA IP核實(shí)現(xiàn)ADC數(shù)據(jù)采集

    本文介紹如何利用FPGADMA技術(shù)處理來自AD9280和AD9708 ADC的數(shù)據(jù)。首先,探討了這兩種ADC的特點(diǎn)及其與FPGA的接口兼容性。接著,詳細(xì)說明了使用Xilinx VIV
    的頭像 發(fā)表于 07-29 14:12 ?5291次閱讀

    RDMA over RoCE V2設(shè)計(jì)2:ip 整體框架設(shè)計(jì)考慮

    設(shè)計(jì)IP需要考慮如下因素: 1)基于 IBTA 1.5 協(xié)議規(guī)范,支持 RoCE v2 標(biāo)準(zhǔn)協(xié)議傳輸,同時(shí)支持 ARP協(xié)議和 ICMP 協(xié)議。 2)基于 Xilinx CMAC 集成塊進(jìn)行開發(fā)并獨(dú)立
    發(fā)表于 07-16 08:51

    NVMe IPAXI4總線分析

    廣泛應(yīng)用 。隨著時(shí)間的推移,AXI4的影響不斷擴(kuò)大。目前,由Xilinx提供的大部分IP接口都支持AXI4總線,使得系統(tǒng)中不同模塊之間的互連更加高效。這也讓基于這些
    發(fā)表于 06-02 23:05

    Xilinx Shift RAM IP概述和主要功能

    Xilinx Shift RAM IP 是 AMD Xilinx 提供的一個(gè) LogiCORE IP ,用于在
    的頭像 發(fā)表于 05-14 09:36 ?1240次閱讀
    收藏| 图们市| 宜兴市| 泗洪县| 鄂尔多斯市| 德化县| 北安市| 达日县| 金乡县| 富锦市| 都兰县| 湘潭县| 汽车| 三穗县| 青阳县| 琼中| 秭归县| 西藏| 柳江县| 门源| 白山市| 禹州市| 广南县| 河东区| 扬中市| 浏阳市| 万山特区| 高青县| 潮安县| 沙雅县| 遵化市| 调兵山市| 芜湖县| 金乡县| 道孚县| 亚东县| 乌恰县| 康保县| 额济纳旗| 昔阳县| 吕梁市|