1. INSTANTIATING LPM in VHDL
To promote LPM usage in VHDL design community, this section describes the syntax for
instantiating LPM in VHDL design file.
1.1 COMPONENT DECLARATION
To instantiate component in VHDL design file, the component has to be declared before use. The
component declaration of LPM modules is defined in the LPM package file in Support Files
section later in this document. In declaring the LPM module, the component should be “fully
described”. Which includes all the optional ports, parameters. Once defined, any number of these
“fully described components” can be instantiated within the VHDL design. For example,
LPM_MULT is declared as the follow:
component LPM_MULT
generic (LPM_WIDTHA : positive;
LPM_WIDTHB : positive;
LPM_WIDTHS : positive;
LPM_WIDTHP : positive;
LPM_REPRESENTATION : string := “UNSIGNED”;
LPM_PIPELINE : integer := 0;
LPM_TYPE: string := L_MULT;
LPM_HINT : string := UNUSED);
port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
ACLR : in std_logic := ‘0’;
CLOCK : in std_logic := ‘0’;
CLKEN : in std_logic := ‘0’;
SUM: in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0');
RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));end component;